Yvan Roux
2015-10-15 21:44:15 UTC
The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2015.10 snapshot of the Linaro GCC 5 source package.
This monthly snapshot[1] is based on FSF GCC 5.2+svn228499 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2015.11
stable [1] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.2-2015.10/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 5.2+svn228499
* Backport of [Bugfix] [AArch32] Fix PR target/29693
* Backport of [Bugfix] [AArch32] PR 52144 Fix ARM/thumb attribute target
* Backport of [Bugfix] [AArch32] PR 52144 Fix ARM/thumb attribute target
* Backport of [Bugfix] [AArch32] PR/63870 Add a __builtin_lane_check
* Backport of [Bugfix] [AArch32] PR/63870 Add qualifier to check lane
bounds in expand
* Backport of [Bugfix] [AArch32] PR 66541, 52144 Fix ARM/thumb pragma target
* Backport of [Bugfix] [AArch32] PR middle-end 64744/48470/43404
* Backport of [Bugfix] [AArch32] PR target/52144 attribute target
(thumb,arm) [2.2/6]
* Backport of [Bugfix] [AArch32] PR target/52144 target attributes
Clean up arm_option_params_internals macro settings for
attribute/pragma targets
* Backport of [Bugfix] [AArch32] PR target/65768
* Backport of [Bugfix] [AArch64] PR63870 Neon error messages for
vldN_lane/vstN_lane
* Backport of [Bugfix] Fix PR66168
* Backport of [Bugfix] Fix PR67280 and Linaro BZ #1765
* Backport of [Bugfix] PR c/49551
* Backport of [Bugfix] PR middle-end/64130
* Backport of [Bugfix] PR middle-end/66726
* Backport of [Bugfix] PR target/65768 Check cost of constants before
propagating
* Backport of [Bugfix] PR tree-optimization/67043
* Backport of [AArch32] 1-ARM/Thumb target attributes
* Backport of [AArch32] 2-ARM/Thumb target attributes
* Backport of [AArch32] 3-ARM/Thumb target attributes
* Backport of [AArch32] Add ARM/thumb attribute target
* Backport of [AArch32] Add ARM/thumb pragma target
* Backport of [AArch32] Add TARGET_OPTION_PRINT
* Backport of [AArch32] attribute target (thumb,arm) [2.1/6]
* Backport of [AArch32] Correct spelling of references to ARMv6KZ
* Backport of [AArch32] Fix ChangeLog
* Backport of [AArch32] fix date
* Backport of [AArch32] Fix static interworking call
* Backport of [AArch32] Fix thinko in use of TARGET_UNIFIED_ASM
* Backport of [AArch32] Fuseable is not a word -> s/fuseable/fusible/g
* Backport of [AArch32] Rename LOGICAL_OP_NON_SC to LOGICAL_OP_NON_SHORT_CIRCUIT
* Backport of [AArch32] Restrict MAX_CONDITIONAL_EXECUTE when
-mrestrict-it is in place
* Backport of [AArch32] Use dmb ish instead of dmb sy for ARM
* Backport of [AArch64] 1/3 ARMv8.1 Use atomic compare-and-swap
instructions when available
* Backport of [AArch64] [1/4] Define candidates for instruction fusion
in a .def file
* Backport of [AArch64] 1/5 Use atomic instructions for swap and
fetch-update operations
* Backport of [AArch64] 2/3 ARMv8.1 Use the atomic compare-and-swap
instructions when available
* Backport of [AArch64] [2/4] Control the FMA steering pass in tuning
structures rather than as core property
* Backport of [AArch64] 2/5 Make BIC, other logical instructions, available
* Backport of [AArch64] 3/3 ARMv8.1 Use the atomic compare-and-swap
instructions when available
* Backport of [AArch64] [3/4] De-const-ify struct tune_params
* Backport of [AArch64] 3/5 Add atomic load-operate instructions
* Backport of [AArch64] [4/4] Add -moverride tuning command, and wire
it up for control of fusion and fma-steering
* Backport of [AArch64] 4/5 Use atomic load-operate instructions for
fetch-update patterns
* Backport of [AArch64] 5/5 Use atomic load-operate instructions for
update-fetch patterns
* Backport of [AArch64] Add ACLE predefined marcos:
__ARM_ALIGN_MAX_PWR and __ARM_ALIGN_MAX_STACK_PWR
* Backport of [AArch64] Add support for ARMv8.1 command line options
* Backport of [AArch64] Always register fma_steering pass but gate it
on the target option instead
* Backport of [AArch64] [armv8.1] Expand +rdma documentation, small
changes to march and mcpu text
* Backport of [AArch64] --with-arch in config.gcc support "."
* Backport of [AArch64] Change %ld to %wd for HOST_WIDE_INT parameter
* Backport of [AArch64] Fix another ICE with -mgeneral-regs-only
* Backport of [AArch64] Fix ICES with -mgeneral-regs-only / -march=...+nofp
* Backport of [AArch64] fix regrename pass to ensure renamings produce
valid insns
* Backport of [AArch64] Fix type of
*<LOGICAL:optab>_one_cmpl_<SHIFT:optab><mode>3 pattern
* Backport of [AArch64] Fuseable is not a word -> s/fuseable/fusible/g
* Backport of [AArch64] Improve spill code - swap order in shl pattern
* Backport of [AArch64] Improve spill code - swap order in shr patterns
* Backport of [AArch64] movi type attribute confusion
* Backport of [AArch64] Removed unused SLOWMUL target flags
* Backport of [AArch64] typo fix in attribute for vst2_lane
* Backport of [AArch64] Use conditional negate for abs
* Backport of [Testsuite] [AArch32] Add -mfloat-abi=softfp to some xscale tests
* Backport of [Testsuite] [AArch32] Disable attr_thumb.c test when
Thumb mode is not supported
* Backport of [Testsuite] [AArch32] Do not override -mcpu in no-volatile-in-it.c
* Backport of [Testsuite] [AArch32] Fix gcc.target/arm/attr_thumb.c
* Backport of [Testsuite] [AArch32] Fix gcc.target/arm/thumb_ifcvt.c
* Backport of [Testsuite] [AArch32] gcc.target/arm/pr65647.c should
not add -mfloat-abi=soft
* Backport of [Testsuite] [AArch32] target attribute cleanup directives
* Backport of [Testsuite] [AArch64] Testsuite check for sqrt_insn
* Backport of [Testsuite] [AArch64] vld1-vst1_1.c: Add missing float32x4_t case
* Backport of [Testsuite] AdvSIMD intrinsics tests cleanup: remove
useless expected values
* Backport of [Testsuite] Don't specify "dg-do run" explicitly for
vect test cases
* Backport of [Testsuite] gcc.target/arm/neon-reload-class.c: Remove
movw and movt
* Backport of [Testsuite] g++.dg/ext/pr57735.C should not run if the
testsuite is explicitly passing -mfloat-abi=hard
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] Skip tests for inappropriate multilibs
* Backport of [Misc] [1] Allow REG_EQUAL for ZERO_EXTRACT
* Backport of [Misc] Set REG_EQUAL
* Backport of [Misc] [2] Allow REG_EQUAL for ZERO_EXTRACT
* Backport of [Misc] Fix ChangeLog
* Backport of [Misc] fix segfault in verify_flow_info() with -dx option
* Backport of [Misc] fix typo
* Backport of [Misc] Fix typo: Rename insn_reservation
cortex_53_advsimd to cortex_a53_advsimd
* Backport of [Misc] Fuseable is not a word -> s/fuseable/fusible/g
* Backport of [Misc] [ifcvt Fix typo in comment
* Backport of [Misc] [match-and-simplify] fix incorrect code-gen in
'for' pattern
* Backport of [Misc] [match-and-simplify] reject expanding
operator-list to implicit 'for'
* Backport of [Misc] [match-and-simplify] report error for invalid
operator-lists
* Backport of [Misc] [simplify-rtx][2/2] Simplify - (y ? -x : x) ->
(!y ? -x : x)
* Backport of [Misc] The comparison in a compare exchange should not
take place in VOIDmode
* Backport of [Misc] Use cinc mnemonic for *csinc2<mode>_insn
* Backport of [Misc] warn for empty struct -Wc++-compat
* Backport of [Misc] [Driver] Wrong C++ paths when configuring with
"--with-sysroot=/"
* Backport of [Misc] [combine][1/2] Try to simplify before substituting
* Backport of [Doc] [AArch64] Clarify feature modifiers {no,}{fp,simd,crypto}
* Backport of [Doc] [AArch64] Fix position of -moverride documentation
* Backport of [Doc] move (Variable Attributes, Type Attributes) up
Feedback and Support
Subscribe to the important Linaro mailing lists and join our IRC
channels to stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:***@linaro.org
[1]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
[2]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
2015.10 snapshot of the Linaro GCC 5 source package.
This monthly snapshot[1] is based on FSF GCC 5.2+svn228499 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2015.11
stable [1] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.2-2015.10/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 5.2+svn228499
* Backport of [Bugfix] [AArch32] Fix PR target/29693
* Backport of [Bugfix] [AArch32] PR 52144 Fix ARM/thumb attribute target
* Backport of [Bugfix] [AArch32] PR 52144 Fix ARM/thumb attribute target
* Backport of [Bugfix] [AArch32] PR/63870 Add a __builtin_lane_check
* Backport of [Bugfix] [AArch32] PR/63870 Add qualifier to check lane
bounds in expand
* Backport of [Bugfix] [AArch32] PR 66541, 52144 Fix ARM/thumb pragma target
* Backport of [Bugfix] [AArch32] PR middle-end 64744/48470/43404
* Backport of [Bugfix] [AArch32] PR target/52144 attribute target
(thumb,arm) [2.2/6]
* Backport of [Bugfix] [AArch32] PR target/52144 target attributes
Clean up arm_option_params_internals macro settings for
attribute/pragma targets
* Backport of [Bugfix] [AArch32] PR target/65768
* Backport of [Bugfix] [AArch64] PR63870 Neon error messages for
vldN_lane/vstN_lane
* Backport of [Bugfix] Fix PR66168
* Backport of [Bugfix] Fix PR67280 and Linaro BZ #1765
* Backport of [Bugfix] PR c/49551
* Backport of [Bugfix] PR middle-end/64130
* Backport of [Bugfix] PR middle-end/66726
* Backport of [Bugfix] PR target/65768 Check cost of constants before
propagating
* Backport of [Bugfix] PR tree-optimization/67043
* Backport of [AArch32] 1-ARM/Thumb target attributes
* Backport of [AArch32] 2-ARM/Thumb target attributes
* Backport of [AArch32] 3-ARM/Thumb target attributes
* Backport of [AArch32] Add ARM/thumb attribute target
* Backport of [AArch32] Add ARM/thumb pragma target
* Backport of [AArch32] Add TARGET_OPTION_PRINT
* Backport of [AArch32] attribute target (thumb,arm) [2.1/6]
* Backport of [AArch32] Correct spelling of references to ARMv6KZ
* Backport of [AArch32] Fix ChangeLog
* Backport of [AArch32] fix date
* Backport of [AArch32] Fix static interworking call
* Backport of [AArch32] Fix thinko in use of TARGET_UNIFIED_ASM
* Backport of [AArch32] Fuseable is not a word -> s/fuseable/fusible/g
* Backport of [AArch32] Rename LOGICAL_OP_NON_SC to LOGICAL_OP_NON_SHORT_CIRCUIT
* Backport of [AArch32] Restrict MAX_CONDITIONAL_EXECUTE when
-mrestrict-it is in place
* Backport of [AArch32] Use dmb ish instead of dmb sy for ARM
* Backport of [AArch64] 1/3 ARMv8.1 Use atomic compare-and-swap
instructions when available
* Backport of [AArch64] [1/4] Define candidates for instruction fusion
in a .def file
* Backport of [AArch64] 1/5 Use atomic instructions for swap and
fetch-update operations
* Backport of [AArch64] 2/3 ARMv8.1 Use the atomic compare-and-swap
instructions when available
* Backport of [AArch64] [2/4] Control the FMA steering pass in tuning
structures rather than as core property
* Backport of [AArch64] 2/5 Make BIC, other logical instructions, available
* Backport of [AArch64] 3/3 ARMv8.1 Use the atomic compare-and-swap
instructions when available
* Backport of [AArch64] [3/4] De-const-ify struct tune_params
* Backport of [AArch64] 3/5 Add atomic load-operate instructions
* Backport of [AArch64] [4/4] Add -moverride tuning command, and wire
it up for control of fusion and fma-steering
* Backport of [AArch64] 4/5 Use atomic load-operate instructions for
fetch-update patterns
* Backport of [AArch64] 5/5 Use atomic load-operate instructions for
update-fetch patterns
* Backport of [AArch64] Add ACLE predefined marcos:
__ARM_ALIGN_MAX_PWR and __ARM_ALIGN_MAX_STACK_PWR
* Backport of [AArch64] Add support for ARMv8.1 command line options
* Backport of [AArch64] Always register fma_steering pass but gate it
on the target option instead
* Backport of [AArch64] [armv8.1] Expand +rdma documentation, small
changes to march and mcpu text
* Backport of [AArch64] --with-arch in config.gcc support "."
* Backport of [AArch64] Change %ld to %wd for HOST_WIDE_INT parameter
* Backport of [AArch64] Fix another ICE with -mgeneral-regs-only
* Backport of [AArch64] Fix ICES with -mgeneral-regs-only / -march=...+nofp
* Backport of [AArch64] fix regrename pass to ensure renamings produce
valid insns
* Backport of [AArch64] Fix type of
*<LOGICAL:optab>_one_cmpl_<SHIFT:optab><mode>3 pattern
* Backport of [AArch64] Fuseable is not a word -> s/fuseable/fusible/g
* Backport of [AArch64] Improve spill code - swap order in shl pattern
* Backport of [AArch64] Improve spill code - swap order in shr patterns
* Backport of [AArch64] movi type attribute confusion
* Backport of [AArch64] Removed unused SLOWMUL target flags
* Backport of [AArch64] typo fix in attribute for vst2_lane
* Backport of [AArch64] Use conditional negate for abs
* Backport of [Testsuite] [AArch32] Add -mfloat-abi=softfp to some xscale tests
* Backport of [Testsuite] [AArch32] Disable attr_thumb.c test when
Thumb mode is not supported
* Backport of [Testsuite] [AArch32] Do not override -mcpu in no-volatile-in-it.c
* Backport of [Testsuite] [AArch32] Fix gcc.target/arm/attr_thumb.c
* Backport of [Testsuite] [AArch32] Fix gcc.target/arm/thumb_ifcvt.c
* Backport of [Testsuite] [AArch32] gcc.target/arm/pr65647.c should
not add -mfloat-abi=soft
* Backport of [Testsuite] [AArch32] target attribute cleanup directives
* Backport of [Testsuite] [AArch64] Testsuite check for sqrt_insn
* Backport of [Testsuite] [AArch64] vld1-vst1_1.c: Add missing float32x4_t case
* Backport of [Testsuite] AdvSIMD intrinsics tests cleanup: remove
useless expected values
* Backport of [Testsuite] Don't specify "dg-do run" explicitly for
vect test cases
* Backport of [Testsuite] gcc.target/arm/neon-reload-class.c: Remove
movw and movt
* Backport of [Testsuite] g++.dg/ext/pr57735.C should not run if the
testsuite is explicitly passing -mfloat-abi=hard
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] New AdvSIMD test
* Backport of [Testsuite] Skip tests for inappropriate multilibs
* Backport of [Misc] [1] Allow REG_EQUAL for ZERO_EXTRACT
* Backport of [Misc] Set REG_EQUAL
* Backport of [Misc] [2] Allow REG_EQUAL for ZERO_EXTRACT
* Backport of [Misc] Fix ChangeLog
* Backport of [Misc] fix segfault in verify_flow_info() with -dx option
* Backport of [Misc] fix typo
* Backport of [Misc] Fix typo: Rename insn_reservation
cortex_53_advsimd to cortex_a53_advsimd
* Backport of [Misc] Fuseable is not a word -> s/fuseable/fusible/g
* Backport of [Misc] [ifcvt Fix typo in comment
* Backport of [Misc] [match-and-simplify] fix incorrect code-gen in
'for' pattern
* Backport of [Misc] [match-and-simplify] reject expanding
operator-list to implicit 'for'
* Backport of [Misc] [match-and-simplify] report error for invalid
operator-lists
* Backport of [Misc] [simplify-rtx][2/2] Simplify - (y ? -x : x) ->
(!y ? -x : x)
* Backport of [Misc] The comparison in a compare exchange should not
take place in VOIDmode
* Backport of [Misc] Use cinc mnemonic for *csinc2<mode>_insn
* Backport of [Misc] warn for empty struct -Wc++-compat
* Backport of [Misc] [Driver] Wrong C++ paths when configuring with
"--with-sysroot=/"
* Backport of [Misc] [combine][1/2] Try to simplify before substituting
* Backport of [Doc] [AArch64] Clarify feature modifiers {no,}{fp,simd,crypto}
* Backport of [Doc] [AArch64] Fix position of -moverride documentation
* Backport of [Doc] move (Variable Attributes, Type Attributes) up
Feedback and Support
Subscribe to the important Linaro mailing lists and join our IRC
channels to stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:***@linaro.org
[1]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
[2]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.