[ACTIVITY] report week ending 21 Sep

[Peter Maydell]

Progress:
This week was Linaro Connect (Vancouver). Recordings are
online for most sessions I think; some may still be in the
process of being uploaded. For other presentations see:
https://connect.linaro.org/resources/yvr18/

Interesting presentations:
* "My other Machine is Virtual"
-- Alex's talk summarising QEMU's current tracing/debug facilities:
https://connect.linaro.org/resources/yvr18/yvr18-118/
* "SBSA QEMU"
-- Summary of work on an "enterprise" model in QEMU intended for use
as a development platform for firmware and other lower-level code.
https://connect.linaro.org/resources/yvr18/yvr18-511/
* "How to build a C++ processing tool using the clang libraries"
-- Peter Smith doing a fast pass through the clang library APIs
you can use for refactoring-type tools that operate on C++ source.
Watch the talk to figure out if this is something you want to
do at all; read the slides separately for the fine detail and
links to where to find more info, if the answer is "yes"...
https://connect.linaro.org/resources/yvr18/yvr18-223/
* "Diary of a drive-by coder: tips and tricks for working with upstream"
-- James Bottomley talks about successes and failures in upstreaming
one-off patches if you're not a member of the community. I also
asked in the Q&A about what communities can do to make life
easier for such contributors (answer mostly revolved around
better and clearer communication about the chances of a change
being accepted)
https://connect.linaro.org/resources/yvr18/yvr18-503/
* "An open source developer and a lawyer walk into a bar..."
-- Jilayne Lovejoy's keynote
(Personal takeaway: try to reduce my use of "IANAL, but...".)
https://connect.linaro.org/resources/yvr18/yvr18-200k2/
* Fujitsu's keynote on their new A64FX CPU:
https://connect.linaro.org/resources/yvr18/yvr18-400k1/
* Arm Architecture Enhancements in 2018
Matt Gretton-Dann's presentation of ARM v8A 8.5 features.
I was particularly encouraged to see that Arm have been able
to make public the system register and ISA XML on the same day
they announce the new features publicly.
https://connect.linaro.org/resources/yvr18/yvr18-104/

Useful meetings:
* discussion with RTH about handling CPU ID register fields
vs internal QEMU "enable this feature" bits (we have a bit of
an ugly mix of specifying the same thing in both places, and
also overriding ID reg fields from feature bits in some cases;
we'd like to achieve a bit more consistency in what we do...)
* discussion with RTH/Alex on instrumentation plugin APIs. I hope
we're now more or less on the same page about the general principles.
* QEMU roadmap sync with Alex/RTH/Maxim:
- finish v8M work
- heterogenous CPU support (for Musca board emulation)
- finish SVE
- fill in other v8.x missing emulation support
- instrumentation work

Other:
* Greensocs have sent out some QEMU patches to do with
modelling clock trees, which also touch a bit on reset.
QEMU's modelling of reset at the moment is pretty terrible,
so I had a think about how we might manage to do it better.
(Notably we currently only model power-on reset, and we don't
have a good answer for "device A in reset wants to assert a
signal that connects to device B, but there's no guarantee
about what order A and B will reset in". Does anybody know of
any good existing treatments of modelling device reset ?)

thanks
-- PMM